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ATmega128
Memory
Programming
Program and Data
Memory Lock Bits
The Atmel ? AVR ? ATmega128 provides six Lock bits which can be left unprogrammed (“1”) or
can be programmed (“0”) to obtain the additional features listed in Table 116 . The Lock bits can
only be erased to “1” with the Chip Erase command.
Table 115. Lock Bit Byte
Lock Bit Byte
BLB12
BLB11
BLB02
BLB01
LB2
LB1
Bit No.
7
6
5
4
3
2
1
0
Description
–
–
Boot lock bit
Boot lock bit
Boot lock bit
Boot lock bit
Lock bit
Lock bit
Default Value
1 (unprogrammed)
1 (unprogrammed)
1 (unprogrammed)
1 (unprogrammed)
1 (unprogrammed)
1 (unprogrammed)
1 (unprogrammed)
1 (unprogrammed)
Note:
“1” means unprogrammed, “0′means programmed
Table 116. Lock Bit Protection Modes
Memory Lock Bits
Protection Type
LB mode
LB2
LB1
1
1
1
No memory lock features enabled.
Further programming of the Flash and EEPROM is
2
1
0
disabled in Parallel and SPI/JTAG Serial Programming
mode. The Fuse bits are locked in both Serial and Parallel
Programming mode. (1)
Further programming and verification of the Flash and
3
0
0
EEPROM is disabled in Parallel and SPI/JTAG Serial
Programming mode. The Fuse bits are locked in both
Serial and Parallel Programming mode. (1)
BLB0 mode
BLB02
BLB01
1
2
1
1
1
0
No restrictions for SPM or (E)LPM accessing the
Application section.
SPM is not allowed to write to the Application section.
SPM is not allowed to write to the Application section, and
(E)LPM executing from the Boot Loader section is not
3
0
0
allowed to read from the Application section. If interrupt
vectors are placed in the Boot Loader section, interrupts
are disabled while executing from the Application section.
(E)LPM executing from the Boot Loader section is not
4
0
1
allowed to read from the Application section. If interrupt
vectors are placed in the Boot Loader section, interrupts
are disabled while executing from the Application section.
BLB1 mode
BLB12
BLB11
286
2467X–AVR–06/11
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